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CY7C1009V33 CY7C109V33
128K x 8 Static RAM
Features
* High speed -- tAA = 15, 20, 25ns * VCC = 3.3V 10% * Low active power -- 432 mW (max.) -- 288 mW (L version) * Low CMOS standby power -- 18 mW (max.) * * * * -- 7.2 mW (L version) 2.0V Data Retention Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE1, CE2, and OE options memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable one (CE1) and Write Enable (WE) inputs LOW and Chip Enable two (CE2) input HIGH. Data on the eight I/O pins (I/O 0 through I/O 7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable one (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE 2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C109V33 is available in standard 32-pin, 400-mil-wide SOJ package. The CY7C1009V33 is available in a 32-pin, 300-mil-wide SOJ package. The CY7C1009V33 and CY7C109V33 are functionally equivalent in all other respects.
Functional Description
The CY7C109V33/CY7C1009V33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy
Logic Block Diagram
Pin Configurations
SOJ Top View
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
I/O0
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8
I/O1
ROW DECODER
I/O2
SENSE AMPS 512 x 256 x 8 ARRAY
109V33-2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 109V33-3
I/O3 I/O4 I/O5
TSOP I Top View (not to scale)
CE1 CE2 WE OE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
A9 A 10 A 11 A 12 A 13 A14 A15 A16
109V33-1
Selection Guide
7C109V33-12 7C109V33-15 7C109V33-20 7C109V33-25 7C1009V33-12 7C1009V33-15 7C1009V33-20 7C1009V33-25 Maximum Access Time (ns) 12 15 20 20 Maximum Operating Current (mA) 130 120 110 110 Maximum Operating Current (mA) Low Power Version 90 80 70 70 Maximum CMOS Standby Current (mA) Standard 5 5 5 5 Maximum CMOS Standby Current (mA) Low Power Version 2 2 2 2
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 September 3, 1999
CY7C1009V33 CY7C109V33
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .....................................-0.5V to VCC +0.5V DC Input Voltage[1] ................................. -0.5V to VCC +0.5V Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range Commercial Ambient Temperature[2] 0C to +70C VCC 3.3V 300mV
Electrical Characteristics Over the Operating Range
7C109V33-12 7C1009V33-12 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. V CC, CE1 > VIH or CE2 < VIL, VIN > V IH or VIN < V IL, f = fMAX Max. V CC, CE1 > VCC - 0.3V, or CE2 < 0.3V, VIN > V CC - 0.3V, or V IN < 0.3V, f=0 L L Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 -1 -5 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 130 90 25 2.2 -0.3 -1 -5 Max. 7C1009V33-15 7C109V33-15 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 120 80 20 mA Max. Unit V V V V A A mA
ISB1
ISB2
5 2
5 2
mA
Shaded areas contain preliminary information. Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature.
2
CY7C1009V33 CY7C109V33
Electrical Characteristics Over the Operating Range (continued)
7C1009V33-20 7C109V33-20 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. V CC, CE1 > VIH or CE2 < VIL, VIN > V IH or VIN < V IL, f = fMAX Max. V CC, CE1 > VCC - 0.3V, or CE2 < 0.3V, VIN > V CC - 0.3V, or V IN < 0.3V, f=0 L L Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 -1 -5 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 110 70 20 2.2 -0.3 -1 -5 Max. 7C1009V33-25 7C109V33-25 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 110 70 20 mA Max. Unit V V V V A A mA
ISB1
ISB2
5 2
5 2
mA
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 6 8 Unit pF pF
Note: 3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) Equivalent to: R2 255 R1 480 R1 480 3V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255 GND 3ns 3.0V 90% 10% 90% 10% 3 ns ALL INPUT PULSES
109V33-4 109V33-5
THEVENIN EQUIVALENT 167 1.73V OUTPUT
3
CY7C1009V33 CY7C109V33
Switching Characteristics[4] Over the Operating Range
7C1009V33-12 7C1009V33-15 7C1009V33-20 7C1009V33-25 7C109V33-12 7C109V33-15 7C109V33-20 7C109V33-25 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[5, 6] CE1 LOW to Low Z, CE2 HIGH to Low Z[6] CE1 HIGH to High Z, CE2 LOW to High Z CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down Write Cycle Time CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[6] WE LOW to High Z
[5, 6] [5, 6]
Description
Min. 12
Max.
Min. 15
Max.
Min. 20
Max.
Min. 20
Max. Unit ns 20 ns ns 20 8 ns ns ns 8 ns ns 8 ns ns 20 ns
12 3 12 6 0 6 3 6 0 12 0 3 0 3
15 3 15 7 0 7 3 7 0 15
20 3 20 8 0 8 3 8 0 20
WRITE CYCLE[7,8] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE 12 10 10 0 0 10 7 0 3 6 15 12 12 0 0 12 8 0 3 7 20 15 15 0 0 15 10 0 3 8 20 15 15 0 0 15 10 0 3 8 ns ns ns ns ns ns ns ns ns ns
Shaded areas contain preliminary information.
Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter VDR ICCDR tCDR tR Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions No input may exceed VCC + 0.5V VCC = V DR = 2.0V, CE1 > VCC - 0.3V or CE2 < 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Min. 2.0 200 0 tRC Max Unit V A ns ns
Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH and 30-pF load capacitance. 5. t HZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
4
CY7C1009V33 CY7C109V33
Switching Waveforms
Read Cycle No. 1[9, 10]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
109V33-6
Read Cycle No. 2 (OE Controlled)[10, 11]
ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB
109V33-7
HIGH IMPEDANCE
ICC
Write Cycle No. 1 (CE1 or CE2 Controlled)[12, 13]
tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tPWE WE tSD DATA I/O DATA VALID
109V33-8
tHA
tHD
Notes: 9. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 12. Data I/O is high impedance if OE = VIH. 13. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
5
CY7C1009V33 CY7C109V33
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 14 tHZOE DATAIN VALID
109V33-9
tHD
Write Cycle No. 3 (WE Controlled, OE LOW)[13]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tSD DATA I/O NOTE 14 tHZWE DATA VALID tLZWE
109V33-10
tHA tPWE
tHD
Note: 14. During this period the I/Os are in the output state and input signals should not be applied.
6
CY7C1009V33 CY7C109V33
Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O 0-I/O7 High Z High Z Data Out Data In High Z Power-Down Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 12 Ordering Code CY7C109V33-12VC CY7C1009V33-12VC CY7C1009V33L-12VC CY7C109V33-12ZC 15 CY7C109V33-15VC CY7C1009V33-15VC CY7C1009V33L-15VC CY7C109V33-15ZC 20 CY7C109V33-20VC CY7C109V33-20ZC CY7C109V33L-20VC CY7C109V33L-20ZC CY7C1009V33-20VC CY7C1009V33L-20VC 25 CY7C109V33-25VC CY7C109V33L-25VC CY7C109V33L-25ZC CY7C1009V33L-25VC CY7C1009V33-25VC
Shaded areas contain preliminary information.
Package Name V33 V32 V32 Z32 V33 V32 V32 Z32 V33 Z32 V33 Z32 V32 V32 V33 V33 Z32 V32 V32
Package Type 32-Lead (400-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead TSOP Type I 32-Lead (400-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead TSOP Type I 32-Lead (400-Mil) Molded SOJ 32-Lead TSOP Type I 32-Lead (400-Mil) Molded SOJ 32-Lead TSOP Type I 32-Lead (300-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead TSOP Type I 32-Lead (300-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ
Operating Range Commercial
Commercial
Commercial
Commercial
Document #: 38-00635-A
7
CY7C1009V33 CY7C109V33
Package Diagrams
32-Lead (300-Mil) Molded SOJ V32
51-85041-A
32-Lead (400-Mil) Molded SOJ V33
51-85033-A
8
CY7C1009V33 CY7C109V33
Package Diagrams (continued)
32-Lead Thin Small Outline Package Z32
51-85056-B
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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